`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/11/05 19:11:51
// Design Name: 
// Module Name: testbench_cnt
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module testbench_cnt();

reg clk;
reg rst;
reg led0;
reg [7:0] random_value;
reg c_rst;
event my_event;
reg [1:0] c_dir;
reg c_stop;
reg rst_ok;
task stop_task;
    begin
        c_stop=1;
    end
endtask

task c_rst_task;
    begin
        c_rst=1;
        #100;
        c_rst=0;
        #100;
        c_rst=1;
    end
endtask

task c_dir_task;
    input [1:0] dir;
    begin
        c_stop= 0;
        c_rst = 1;
        c_dir=dir;
    end
endtask


initial begin
c_dir=1;
c_stop=0;
c_rst=0;
     wait(rst_ok==1);
     #300;
     c_rst_task();
     #300;
     c_dir_task(2);
     #1000000;
     $stop;
end
initial begin
    #5->my_event;
end

always@(my_event)begin
    $display("ksgksgkgskgskgskgsksgksgksgsk");
end

always #5 clk = ~clk;

initial begin
    random_value=$random;
end
//时钟和复位
    initial begin
        rst_ok=0;
        clk = 0;
        rst = 1;
        #100;
        rst=0;
        #100;
        rst=1;
        rst_ok=1;
    end
//测试display的功能
    initial begin
        #1000;
        $display("At time %t, clk = %b, rst = %b", $time, clk, rst);
        $display("AGAGAGAGAGAGAGAGGGAGAGAGAGAGGAGAGGAG");
        $display("simulation finish");
    end
    
     initial begin
        $monitor("At time %t, clk = %b, rst = %b", $time, clk, rst);
    end
    
    initial begin
           wait(led0==1);
           $display("led0==1");
           $stop;
    end
    
    initial begin
        @(posedge clk);
        $display("5ns come");
    
    end
    
 counter_top_2class u_counter_top_2class(
   .clk     (clk    ),
   .rst     (rst    ),
   .c_rst   (c_rst  ),
   .c_stop  (c_stop ),
   .c_dir   (c_dir  ) //1向上，0向下
 );
//led_digital_top u_led_digital_top(
//    .clk    (clk),
//    .rst    (rst),
//    .sw1    (),
//    .led0   (led0),
//    .led1   (led1),
//    .led2   (led2),
//    .led3   (led3) 
//    );
endmodule
